1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) and a pulse adjustment circuit thereof.
2. Descriptions of the Related Art
With the rapid development of consumer electronic technology, people are becoming accustomed to using various electronic products, such as electronic multimedia products. One key component of multimedia electronic products is the display. Since liquid crystal displays (LCDs) have properties such as radiation-free, low power consumption, a plane square shape, high resolution, and stable display quality, LCDs have gradually replaced the traditional cathode ray tube displays (CRT displays). Consequently, the LCD is widely used as a display panel of electronic products such as cellular phones, display screens, digital televisions, and notebooks.
Generally, the LCD display panels comprise a plurality pixels arranged in an array. The display panel further comprises an active matrix driving circuit for controlling the operations of each pixel of the display panel. Each pixel comprises a thin film transistor (TFT), which functions as a switch.
The conventional TFT has three terminals: the gate, source and drain. The gate and source/drain of the TFT of each pixel are coupled to a scan line and a data line, and the two lines are orthogonal to each other. The active matrix display panel comprises an active matrix driving circuit which comprises a plurality of scan lines and data lines thereby. The scan line is driven by a gate driver, which is used to provide a gate signal to an associated TFT. The data line is driven by a source driver, which is used to provide data signals to the pixels.
To reduce the cost and the dimension of the LCD, the industrial field provides a different driving technology, mainly, the multi-switch half source driving (MSHD) technology which effectively decreases the number of source drivers to half of those in the prior art. In the conventional driving method, the charge time is determined by the width of a gate clock (GCK). When adopting MSHD technology, the charging time is reduced by half and also reduced the source to half in comparison to the conventional one. FIG. 1A illustrates the circuit of the conventional MSHD technology, while FIG. 1B is the waveform chart of a gate driving signal. The gate driving signal comprises a first pulse 11, a second pulse 13, and a third pulse 15, which are repeated in order. The first pulse 11 has a longer duty cycle, while the second pulse 13 and the third pulse 15 have a shorter duty cycle.
In FIG. 1A subpixels A, B, C, D and E, are used to illustrate the principle of operation with respect to the MSHD circuit. The drains of some subpixels' TFTs are connected to the data line, while the gates of these subpixels' TFTs are connected to the scan lines Gn, Gn−1, and Gn+1. The sources are grounded via a liquid capacitance CLC and are connected to the drains of other subpixels. The sources of the subpixels A and C are connected to the drains of the subpixels B and D, respectively. The gates of the subpixels B and D are connected to scan lines Gn−1, and Gn, respectively. The sources of subpixels B and D are grounded after connecting with the liquid capacitances CLC. In the direction parallel to the data lines, the subpixels A, C, and E are defined as odd pixels, while the subpixels B and D are defined as even pixels.
In FIG. 1B, GCK stands for the clock signal of the gate driving signal. The gate driving signal, comprising the first pulse 11, the second pulse 13, and the third pulse 15, requires two clock cycles of time. The positive edge of the first pulse 11 occurs at the same time with the positive edge of the clock, while the negative edge of the first pulse 11 occurs earlier than the negative edge of the clock. The positive edge of the second pulse 13 occurs at the same time with the positive edge of the next clock, while the negative edge of the second pulse 13 occurs earlier than the negative edge of the next clock. The positive edge of the third pulse 15 occurs at the same time with the negative edge of the next clock, while the negative edge of the third pulse 15 occurs earlier than the positive edge of a further next clock. The timings of both adjacent scan lines differ by one pulse cycle, which means that the positive edge of the second pulse 13 of the scan line Gn−1 and the positive edge of the first pulse 11 of the scan line Gn occur at the same time, and so on.
The alphabets in the following table represent the subpixels which are turned on for writing, i.e. charging, a data voltage, and the bold, italicized, and underlined alphabets represent the subpixels to which the data lines the data voltages will be supplied. In FIG. 1B, when the timing is T1, the gate line Gn and the gate line Gn−1 are turned on simultaneously, so the subpixels A, B and E are charged at the same time. However, the voltage charged by the data line is configured to supply the subpixel B and other subpixels, and the subpixels A and E will be written in with the right voltages at following timings.
Furthermore, when it is at the timing T1 to write the data onto the subpixel B via charging, the scan lines Gn and Gn−1 should be at the high level. At this time, the signals that are inputted to the scan lines Gn and Gn−1 are at the first pulse 11 and the second pulse 13, respectively. When it is at the timing T2 to write the data onto the subpixel E via charging, the scan line Gn−1 should be at the high level, and the signal that is inputted to the scan line Gn−1 is at the third pulse 15. By the same analogy, the third pulse is at the high level when the data voltage is charged onto the odd subpixels, while the first pulse 11 and the second pulse 13 are at the high level when charging the data voltage to the even subpixels. The data voltage is then written to the subpixels B, E, D, A and C in the sequence according to the timings of T1, T2, T3, T4, and T5.
timingT1T2T3T4T5ChargedA,  , E A, C,    subpixel
However, the MSHD driving technology would make the feedthrough voltages of the two adjacent subpixels different, and result in the final voltage difference between the odd subpixels and the even subpixels due to the turn-on times of the TFTs 117 of the two adjacent subpixels are different, as shown in FIG. 1C. The TFTs 117 of the odd subpixel and even subpixel are both affected by the feedthrough voltages at one time. The voltage stored in the liquid crystal capacitances CLC of the even subpixels, however, is affected by the liquid crystal capacitances CLC of the odd subpixels when the charging of the odd subpixels has been stopped. The voltage stored in the liquid crystal capacitances CLC of the even subpixels is halved, while the other half of the voltage is provided to charge the liquid crystal capacitances CLC of the odd subpixels. In the end, the final voltages of the two adjacent subpixels are different, the charged data voltages in the subpixels are different, and thus, the brightness of all the colors in the subpixels is uneven enough that the display performance is affected.
Consequently, it is important to decrease the feedthrough voltage difference between the adjacent subpixels and to improve the display performance of the TFT LCD which adopts the MSHD driving circuit technology.